The present invention relates to a latch circuit for transmitting a pulse signal, a shift register circuit having this latch circuit and an image display device employing this shift register circuit, as well as a logical circuit for performing a logical operation of an input signal capable of performing a normal logical operation of an input signal having a smaller amplitude than a supply voltage of the logical circuit.
Herein is provided a description for a conventional liquid crystal display device and a shift register circuit that constitutes the data signal line drive circuit and scanning signal line drive circuit of the device, which are taken as examples of an image display device and a shift register circuit having the conventional latch circuit. It is to be noted that the shift register and the image display device of the present invention are limited neither to the above liquid crystal display device nor to the shift register for the liquid crystal display device and is able to be applied to an image display device and a shift register for the image display device of another type.
Conventionally, as the above liquid crystal display device, there has been known a liquid crystal display device of an active matrix driving system. As shown in FIG. 37, this liquid crystal display device is constructed of a pixel array ARY, a scanning signal line drive circuit GD and a data signal line drive circuit SD. In the above pixel array ARY, pixels PIX are arranged in the vicinity of intersections of a number of scanning signal lines GL and a number of data signal lines SL that intersect each other and connected to the adjacent scanning signal line GL and data signal line SL so as to be arranged in a matrix form.
The data signal line drive circuit SD samples an input video signal dat in synchronization with a timing signal such as a clock signal cks and writes the resulting data into the data signal lines SL while amplifying the signal as the occasion demands. The scanning signal line drive circuit GD successively selects the scanning signal lines GL in synchronization with a timing signal such as a clock signal ckg, writes the video signal (data) dat written in the data signal lines SL into the corresponding pixels PIX by controlling the opening and closing of switching elements existing in the pixels PIX and holds the data written in the pixels PIX.
As shown in FIG. 38, each pixel PIX is constructed of a field-effect transistor SW that serves as the aforementioned switching element and a pixel capacity comprised of a liquid crystal capacity CL and an auxiliary capacity (added as the occasion demands) CS. Then, the data signal line SL and one electrode of the pixel capacity are connected to each other via the drain and source of the transistor SW, while the gate of the transistor SW is connected to the scanning signal line GL. Further, the other electrode of the pixel capacity is connected to a common electrode (not shown) common to all the pixels. In the above construction, the transmittance or reflectance of the liquid crystals is modulated by a voltage applied to the liquid crystal capacity CL, thereby driving the pixel for display.
A method for writing the aforementioned video signal dat into the data signal lines SL will be described next. As a system for driving the data signal lines SL, there are existing a dot sequence driving system and a line sequence driving system, and reference is herein made to the dot sequence driving system. FIG. 39 shows a detailed circuit diagram of the data signal line drive circuit SD. The video signal dat inputted to a video signal line DAT is written into the data signal line SL by opening and closing a sampling circuit AS by means of an output pulse of each stage of a shift register circuit 1 synchronized with this video signal dat.
Describing the above more concretely, a signal of a sequence of output signals n of adjacent latch circuits SR constituting the shift register circuit 1 is amplified by a buffer circuit constructed of a plurality of inverter circuits, and an inversion signal is generated as the occasion demands to output a sampling signal s and its inverted signal /s to the sampling circuit (analog switch) AS. Then, the sampling circuit AS executes switching based on the sampling signals s and /s to supply the video data from the video signal line DAT to the data signal line SL. The clock signals cks and /cks to the latch circuits SR, output signals n1 through n3 of the latch circuits SR and sampling signals s1 and s2 in the above case are shown in FIGS. 40A through 40G.
FIG. 41 shows a detailed circuit construction of the scanning signal line drive circuit GD. In this scanning signal line drive circuit GD, the signal of the sequence of the output signals n of adjacent latch circuits SR that constitutes a shift register circuit 2 is obtained by NAND circuits, and by further taking an overlap with an external pulse width control signal gps, the desired pulse width is obtained. The clock signals ckg and /ckg to the latch circuits SR, the output signals n1 through n3 of the latch circuits SR, the pulse width control signal gps and scanning signals g11 and g12 to the scanning signal lines GL in the above case are shown in FIGS. 42A through 42H.
In this case, each latch circuit SR that constitutes the shift register circuits 1 and 2 in the data signal line drive circuit SD and the scanning signal line drive circuit GD has a construction as shown in FIG. 43. It is to be noted that FIG. 43 is an example of the latch circuit SR for constituting the shift register circuits 1 and 2 that can execute scanning only in one direction. In this case, a concrete construction example of a clocked inverter circuit 3 employed in the latch circuit SR is shown in FIG. 44. By contrast, when constituting a shift register circuit that can execute bidirectional scanning, a latch circuit SR as shown in FIG. 45 is employed. Either of these latch circuits SR is a half latch circuit, which latches the input signal with either one of the leading edge or the trailing edge of the clocks ck and /ck, outputs the output signal n of a pulse width of one cycle of the clocks ck and /ck.
In order to achieve the compacting, higher resolution, reduction in mounting cost and so on of liquid crystal display devices, a technique for integrally forming the pixel array ARY and the signal line drive circuits SD and GD, which manage the display, on an identical substrate is attracting a great deal of attention. In such a drive circuit integrated type liquid crystal display device, a transparent substrate must be employed as a substrate when constituting a transmission type liquid crystal display devices that are currently widely used. In the above case, it is often the case where a polysilicon thin-film transistor that can be formed on a quartz substrate or a glass substrate as an active element such as a transistor constituting the transistor SW of the pixel PIX or the clocked inverter circuit 3.
However, the aforementioned conventional liquid crystal display device has the problems as follows. That is, as shown in FIG. 39, the data signal line drive circuit SD obtains the sampling signals s and /s on the basis of the signal of the sequence of the output signals n of adjacent two latch circuits SR. Therefore, as shown in FIGS. 40A through 40G, the trailing edge of the sampling signal s1 corresponding to the adjacent data signal line SL1 and the leading edge of the sampling signal s2 corresponding to the adjacent data signal line SL2 roughly coincide with each other.
Therefore, if the waveforms of the sampling signals s and /s become dull or a slight deviation occurs in terms of timing between output signals n from adjacent two latch circuits SR as a consequence of a characteristic change of the transistors that constitutes, for example, the data signal line drive circuit SD, then there is the possibility of the occurrence of overlap between the sampling signals s1 and s2 corresponding to the adjacent data signal lines SL1 and SL2. In such a case, a noise is imposed on the data signal line SL, leading to a concern about the occurrence of troubles such as blur, ghost and crosstalk of the display image.
In the aforementioned conventional liquid crystal display device, the clock signals cks and ckg and start signals sps and spg and so on inputted to the shift register circuits 1 and 2 are externally directly inputted as signals of the same amplitudes as those of the power voltages of the drive circuits SD and GD, as exemplified by the clock signals cks and ckg shown in FIGS. 40A through 40G and FIGS. 42A through 42H. By contrast, in the drive circuit integrated type liquid crystal display device employing the polysilicon thin-film transistors, the transistor characteristics are inferior to those of the monocrystal silicon transistor, and in particular, the threshold voltage has a high absolute value of 1 V to 6 V. Therefore, the drive power voltage cannot help being increased up to 15 to 20 V. Therefore, in the case of the drive circuit integrated type liquid crystal display device, the clock signals cks and ckg and the start signals sps and spg and so on, which are externally directly inputted, are required to have an increased amplitude.
However, if the clock signals cks and ckg have an increased amplitude, then there occurs the problem that the consumption of power increases in the external circuits such as a control circuit (not shown) for generating the clock signal and the like. Furthermore, unwanted emission from the signal lines becomes a serious problem.
In order to solve the problem due to the increase in amplitude of the clock signals cks and ckg and so on as described above, it is proposed to mount a level shifter circuit (signal boost circuit) on the signal line drive circuits SD and GD side of the liquid crystal display device, thereby reducing the voltages of the input/output interfaces.
FIG. 46 shows the data signal line drive circuit SD mounted with the above level shifter circuit. In the data signal line drive circuit SD shown in FIG. 46, a level shifter circuit LS is arranged immediately before the shift register circuit 5. Then, the inputted clock signal cks and start signal sps are supplied to the shift register circuit 5 with their amplitude (5 V) boosted to 15 V. Thus, the operating voltage of 15 V is obtained with the input voltage of 5 V. However, when the polysilicon thin-film transistor is employed in this construction, the duty ratio of the boosted signal largely varies to cause a variation in terms of timing and amplitude of the output pulse n of the data signal line drive circuit SD due to its characteristic variation, and this may incur a reduction in image quality as a consequence of the superimposition of noises on the data signal line SL. Furthermore, since the driving capability of the level shifter circuit LS itself is low, there is necessitated a buffer for driving the subsequent signal lines, also causing the problem that the consumption of power increases.
FIG. 47 shows the scanning signal line drive circuit GD mounted with the aforementioned level shifter circuit. In the scanning signal line drive circuit GD shown in FIG. 47, the level shifter circuit LS is arranged immediately before the shift register circuit 6 and on a pulse width control signal line GPS. Then, the inputted clock signal ckg, start signal spg and pulse width control signal gps are supplied to the shift register circuit 6 or a NOR circuit with their amplitude (5 V) boosted to 15 V. Also in this case, there are the concern about a reduction in image quality and the problem of an increase in consumption of power, similar to the case of the data signal line drive circuit SD mounted with the level shifter circuit LS.
FIG. 48 and FIG. 49 are concrete circuit diagrams of the aforementioned level shifter circuit LS. In the figures, the reference numerals M1 and M2 denote p-type transistors, while the reference numerals M3 through M6 denote n-type transistors. FIG. 50 shows the waveforms of input signals in and /in and output signals out and /out of the level shifter circuit LS shown in FIG. 48 or FIG. 49.
As a method for removing the concern about the reduction in image quality and the problem of the increase in consumption of power, there is a method for providing each of the shift register circuits that constitute the signal line drive circuits SD and GD with a boosting function. According to this method, by virtue of the provision of the boosting function in the latch circuit of each stage that constitutes the shift register circuit, there is no need for a signal line driving use buffer for driving the signal lines between individual latch circuits. Furthermore, since the outputs of the individual latch circuits are directly boosted instead of boosting the control signals such as the clock signal and the start signal which are inputted to the latch circuits, there can be obtained output pulse signals such as the sampling signals s and /s that are stable with respect to the characteristic variation of the transistors.
Note that, in the aforementioned level shifter circuit LS, the transistors into which the clock signals in and /in are inputted are required to have a high driving power because of the structures shown in FIG. 48 and FIG. 49. This causes another problem that the transistors have an increased gate area and the consequent increase in load and consumption of power of the clock signal line.